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changes.mady.by.user Urs Graf

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changes.mady.by.user Michael Zimmerli

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Key Features

  • XC7Z010-1CLG400C

  • 33.33 MHz oscillator

  • 1 GB of DDR3 SDRAM

  • 128 Mb of QSPI Flash

  • Micro SD card interface

  • 10/100/1000 Ethernet

  • USB 2.0

  • USB-UART

  • 100 User I/O (50 per connector)

  • Configurable as up to 48 LVDS pairs or 100 single-ended I/Software

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titleManuals
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titleProgramming Adapter

Design Considerations

The board can be powered by the USB connection. For this, your USB must be able to deliver 500mA. In that case the power banks of the FPGA will not be powered.






Zynq 7000 FPGA Configuration

Section

Processing System

In the OST linux image for the Microzed board, the Zynq 7000 processing system includes the following peripherals:

  • Ethernet
  • SD Card
  • USB
  • UART (over micro usb)
  • I2C 
FPGA PinI2CChannel
MIO 10I2Cscl
MIO 11sda

Programmable Logic

In addition to flink, XADC is also implemented in the PL as an AXI bus component. In addition to internal measurements, it also has I/O interfaces for external measurement.

FPGA PinXADC DeviceChannel
E17XADC0[p]
D180[n]
M191[p]
M201[n]
L192[p]
L202[n]
B193[p]
A203[n]


Flink Configuration 

  • Java
, see https://deepjava.org/. This is a compiler which translates Java directly to highly efficient machine code. A small operating system together with a board support package allows for fast and realtime applications.
  • Python running on Linux. The powerful Python library together with custom built functions in the FPGA can be used for a broad field of embedded systems.
    • Choose a
    • : choose a bit-file to load the programmable logic part (PL) or a mcs-file to load the flash. The msc file contains the bit-file together with a first stage boot loader. See https://deepjava.org/first_example for how to use these files on the Avnet MicroZed board. The files can be found in the deep runtime library under /rsc/
    • .
    • Python running on Linux: the appropriate bit-file has to be built into the Linux image.
    configu-ration
    configuration
    bit-filemcs-fileflink configurationpin mapping
    flink1flink1.bitBOOTflink1.mcsInfo Device, Description = ZedFlink 1 01.12.2023 (left adjusted)mapping
    GPIO Device, 89 channels
    external ADC128S102 Device, 8 ADC channels
    external AD7476 Device, 1 ADC channel
    flink2
    e.g. used for
    SysP
    REALflink2.bitBOOTflink2.mcsInfo Device, Description = ZedFlink 2 01.12.2023mapping
    GPIO Device, 24 channels
    PWM Device, 24 channels
    FQD Device, 8 channels
    PPWA Device, 1 channel
    external ADC128S102 Device, 8 ADC channels
    TCRT1000 Sensors with external ADC AD7476 Device
    UART Device, 2 channels
    Watchdog Device
    XADC Device, 4 channels (no flink component)
    flink3flink3.bitBOOTflink3.mcsInfo Device, Description = ZedFlink 3 01.12.2023 (left adjusted)mapping
    GPIO Device, 4 channels
    external ADC128S102 Device, 8 ADC channels
    external AD5668 Device, 8 DAC channels
    flink4flink4.bitBOOTflink4.mcsInfo Device, Description = ZedFlink 4 7.12.2021 (left adjusted)mapping
    FQD Device, 2 channels
    external ADC128S102 Device, 8 ADC channels
    external AD5668 Device, 8 DAC channels